Conventional approaches for verifying analog signals either (i) run a full-chip analog simulation, subsetting the analog blocks into smaller design blocks, or (ii) run layout versus schematic (LVS) simulations during final processing stages.
Such conventional approaches have several disadvantages. A full-chip analog simulation is very time consuming, difficult to setup, and may not even be possible for large designs. For large designs, when applicable, smaller subsets of the design can be created. The design subsets can be of a manageable design size. The smaller design subsets generally can be fully simulated within an analog simulator. However, the design subset approach requires extra, potentially error-inducing steps. The errors can be introduced in an effort to make a smaller design subset that includes all of the necessary functionality. Furthermore, the process of creating the smaller design subsets must be continually repeated, increasing the overall design effort.
LVS simulations can be implemented to verify analog connectivity. However, LVS simulators have severe drawbacks. Any errors found are expensive (in terms of decision schedule) to correct, since LVS simulation is implemented late in the file verification process. LVS only verifies a layout against a schematic. If the same error is introduced in both the schematic and the layout, the LVS approach will not detect the error.